High performance computing devices often include multiple devices operating in different clock domains, wherein the clock frequency of each clock is independently adjustable. A single processor may include multiple cores communicatively coupled to multiple noncore components, such as a memory controller, I/O interfaces, and others. Each core may operate in a separate clock domain, and the cores may operate in a separate clock domain from the noncore components. Interfaces have been developed for enabling effective communication between different clock domains.
The clock frequency operating within a specific clock domain can be adjusted for various reasons, such as to save power, for thermal protection, and others. In a typical throttling arrangement, the clock frequency of a core can be reduced to reduce the amount of generated heat. Changing the clock frequency tends to be a long process. This is due, in part, to the design of the phase-lock loop (PLL) used to generate the clock frequency and, in part, to the process for maintaining data integrity at the interface between the clock domains.